| 摘要 |
PURPOSE:To improve the accuracy of conversion by forming a signal set to a high level only during a period corresponding to each digital signal of plural bits within the period of one period of a pulse signal having the largest weight among pulse signals. CONSTITUTION:When only an input digital signal D1 is set to a low level and remaining signals D2-D4 are set to a high level, a coincident output signal from a comparator circuit 131 is brought into a high level only during a period when both signals D1 and Q1' are at low level, and a dissident output signal is brought into a low level normally. Since an output signal of an NAND gate 31 in a signal set circuit 14 is brought always to a low level, the high level period is eliminated by the share of the pulse width of the pulse signal Q1' from the output signal from the signal setting circuit 14 in this case in comparision with the case that all the digital signals D1-D4 are set to a high level. |
