| 摘要 |
PURPOSE:To enable a highly accurate measurement of frequency even with a short input pulse width by providing a multiplying circuit at the input stage of a plurality of channels to make the output of an I/Q phase discrimination circuit proportional to the delay time and the multiple order of frequency. CONSTITUTION:A high frequency signal at a terminal 1 is fed to I/Q phase discrimination circuits 6a-6c through distributors 3 and 4a-4c and a delay circuit 5a. I and Q video outputs of a circuit 6a of the first channel (ch) change in proportion to the carrier frequency of an input signal with one cycle being an inverse number (1/gamma) of the delay time. As the input signal distributed to the second - Nth chs is multiplied in the frequency with 2<n-1> multiplying circuits 30b-30c, I and Q video outputs of circuits 6b-6c change in proportion to the input carrier frequency. Therefore, the cycle of the I/Q video will be 1/2-1/2<n-1>. gamma respectively in the second - Nth chs and hence the same results obtained as those when the delay line is multiplied by 2-2<n-1> fold. Sampling pulses of all the chs are so arranged as to generate at gamma+DELTAgamma with the arrival time of the input signals as reference and thus, the I and Q quantization outputs of the overlap time of non-delay signals and delay signals of the chs are sampled and held to obtain a digital output.
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