| 摘要 |
PURPOSE:To provide an adder reduced at the number of logical stages and having a simple circuit by providing the adder with a means for receiving bits from operands to respective cells and a means for receiving an intermediate binary tree value. CONSTITUTION:A cell 100 of a full adder has a group of input wires 115 and a group of output wires 125 and input wires A0, A1 connect the input wires 115 with a logical box 175. Wires B0-G1 connect the input wires 115 with the output wires 125 and other cells also have the same constitution. The input wires 115 and the output wires 125 transmit intermediate tree values. The input wires 115 are used by a carry-in logical box 130 to discrimination whether the cell 100 has a carry-in signal or not. To discriminate a value for the output wires 125, the input wires 115 are also used for the cell 100. The output wires 125 are used as one group of input wires 215 of a cell 200.
|
