发明名称 MEMORY CONTROL CIRCUIT
摘要 PURPOSE:To use effectively an address space of a memory by connecting plural memories of small units and constituting a titled circuit in such a way that a row address of each memory can be specified by a counter. CONSTITUTION:A code signal CS1 is latched by a latch circuit 22. A two-bit counter 23 is cleared by a start pulse P1, a clock CK1 is counted from the initial condition, and a nine-bit shift register 25 is loaded. A carrier output from the counter 23 is utilized as a clock and memories M1-M9 are sequentially set to the readout condition. Data of one character is outputted to a data bus BU3 by such data reading. In order to read out data of one character, the code signal CS1 specifies addresses in the entire memories M1-M9, a row address of each memory is automatically renewed by the register 25 and the counter 23 in sequence, thereby obtaining data of 9X4 bits =36 bits. Thus an address space in a memory can be used effectively.
申请公布号 JPS60182587(A) 申请公布日期 1985.09.18
申请号 JP19840039504 申请日期 1984.03.01
申请人 TOSHIBA KK 发明人 KARIYAMA CHIHARU
分类号 G06F3/12;G06F12/04;G06F12/06;G06K15/00;G09G5/22;G11C7/00 主分类号 G06F3/12
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