| 摘要 |
PURPOSE:To attain high processing speed and high accuracy by subtracting a voltage corresponding to the 1st code from an input voltage, amplifying the result and adding a code multilied to the 1st code by 2N<-1> and the 2nd code obtained by applying the amplified voltage to an A/D converter. CONSTITUTION:Suppose that the relation of Equation I exists with a negative input voltage Vi and VGND=0. When the level of comparators CP1-CP6 is logical ''0'' with an input voltage satisfying the condition Equation I, an output of the parallel A/D converter goes to a negative full scale and 110. As the 1st code for addition, 101 is stored in an adding means 105. Then an output voltage of an amplifier A101 is calculated by using the charge conservation law, an output expressed in Equation II is obtained and a voltage being four times the voltage higher than the input voltage is outputted. Then an S101 is opened and an S102 is closed, and the A/D converter is activated so as to obtain the 2nd code three-bit, and the A/D conversion is five-bit is obtained by operating twice the A/D converter of three-bit accuracy through the addition of the 2nd code to a binary code 10100 through the 4 times multiple of the 1st code.
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