| 摘要 |
PURPOSE:To attain accurate byte synchronization by providing a comparator comparing a content of a memory with an output of a counter and outputting a detection signal when the both are coincident. CONSTITUTION:A control pulse of H level is impressed to a terminal 10. When coincidence of each output is detected for latch circuits 31-33 in the comparator 11, a signal of L level is extracted from the comparator 11. Thus, an output of a NAND gate 12 goes to an L level and an output of a NAND gate 13 goes to an H level, and a signal of H level is extracted from a NOR gate 14, fed to a memory 8 via an OR gate 15, an output of a frequency divider 7 is written in the memory 8 and a framing code detecting pulse is extracted from a terminal 9. In this case, since the comparator 11 detects the point of time when each output of the circuits 31-33 is coincident, the detected pulse has an accurate timing.
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