| 摘要 |
PURPOSE:To enable the realization of the titled IC of short delivery time and low cost under micro formation of patterns by a method wherein the processes to providing contact holes in a resist layer of the first layer are made by the master process. CONSTITUTION:Diffused layers 2, 2,..., poly Si layers 3, 3,..., and an interlayer insulation film 4 are formed on a substrate 1; thereafter, a resist 10 of the first layer is applied. The contact mask having a hole pattern is positioned, and a resist pattern of the first layer is formed by exposure, development, and resist bake. After the first layer resist 10 is coated with the second layer resist 12, the second contact mask is positioned only in the region of contact hole formation. The hole pattern is designed larger than the first one. This manner reduces the custom mask and facilitates the preparation of the masks because of no inclusion of masks such as custom mask steppers. Accordingly, the delivery time of manufacturing the titled IC is shortened, and the manufacturing cost is reduced. |
