| 摘要 |
In a dynamic MOS memory, e.g. a RAM, the charge on the capacitor of a reference cell is restored following a read or refresh operation by coupling a reference voltage generator to the RAM bit line. The generator produces the reference voltage at the output of a buffer whose input is coupled to two capacitors after these have been charged to different voltages and their charges shared. The arrangement allows for transistor thresholds without requiring bootstrapping, is insensitive to manufacturing process variations in that all of the capacitors can be similar, provides for enhanced operation speed, and provides for qualitative signal margin analysis.
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