| 摘要 |
PURPOSE:To improve current interrupting capability by arranging a high life time region to a section near by a current collecting section for a gate electrode and a low life time region to a far section in a plane manner. CONSTITUTION:N-P-N-P structure is formed to a semiconductor substrate 1, and low life time regions 5 are shaped to sections far from a current collecting section 4-1 for a gate electrode 4 and a high life time region 6 to a near section. Since the life time of carriers in the regions 5 is set to a short value, the sections far from the section 4-1 are interrupted at the initial stage of a turn- OFF. The life time of carriers in the region 6 is set at a long value, and current distribution at the latter stage of the turn-OFF determining current interrupting capability concentrates to the section near by the section 4-1 having high supply capability of gate reverse currents, thus improving current interrupting capability. |
