| 摘要 |
Disclosed herein is a method enabling the use of four or more levels of metal over silicon chips whereby increased wiring density, reduced wiring capacitances and improved interconnection reliability are achieved. Stud vertical wiring and special etching procedures to accommodate differences in stud elevation and in stud size, are features which provide substantial planarity in the successive levels. More particularly, the present method includes steps for: the "lift-off" deposition of metal studs on metal wires resulting from the patterning of the layer of the first level of metallization, deposition of a first insulating layer of a material such as silicon dioxide, planarization of said first layer using a standard etch back technique with a planarization medium, until the most elevated stud is exposed, then deposition of a second insulating layer of a material such as silicon nitride over the structure and the etching of the insulator with the same mask pattern that was used to delineate the studs, in order to expose all of the remaining studs. |
