| 摘要 |
PURPOSE:To prefetch efficiently instructions and to prevent the discontinuation of supply of instructions to a pipeline by providing a read register, to which a micro instruction is set, and one or plural registers to which the instruction is set from the read register. CONSTITUTION:In case of an instruction where fetch and store are executed alternately plural times in one instruction, the micro instruction read out from a control memory CS 3 is set to a read register (CSDR0) 32. Next, the micro instruction for store is set from the CS 3 to the CSDR0 32, and simultaneously, contents of the CSDR0 32 which are the previously read instruction for fetch are set to a register 33. Consequently, contents of the CSDR0 32 after setting are the instruction for store, and contents of a CSDR1 33 are the instruction for fetch, and the store operation is executed. If the CSDR0 32 executes always the instruction set to the CSDR0 32 itself, fetch and store are executed alternately plural times.
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