| 摘要 |
PURPOSE:To reduce power consumption by using a latch circuit and a delay gate to generate a drive signal of the final stage inverter of a C-MOS inverter buffer thereby obtaining forcibly a period when both transistors (TRs) are turned off simultaneously at the level transition of an input signal and preventing an excess current between a power supply and common. CONSTITUTION:An input signal A is two inputs of a latch circuit directly and via an inverter 11, and the latch circuit consists of two NOR gates 5, 8 and four inverters 6, 7, 9, 10. An output of the NOR gate 5 is a signal B via the gates 6, 7 and becomes a drive input to a TR21. An output of the NOR gate 8 is inverted to be a signal D by the gate 9 and the signal D is a drive input to a TR22. The gates 6, 7 and 9, 10 constitute respectively latch delay elements and also an intermediate buffers to the final stage inverter 3, the delay function of the gates 6, 7, 9, 10 eliminates the simultaneous on-state of both the TRs at level transition of the input signal thereby preventing a through-current. |
