| 摘要 |
PURPOSE:To prevent deterioration in a frequency characteristic even with an increased tap number by inserting one or plural gate electrodes of the titled device in which a DC bias voltage is applied to a tap addition part. CONSTITUTION:The size of storage gate electrodes 15, 15a in the charge transfer direction to which a transfer clock phi1 is applied is decreased to prevent the deterioration in the transfer efficiency at the tap addition part. Then a gate electrode 60 to which a DC bias voltage VB is applied is inserted between the gate electrodes 15, 15a and a transfer gate electrode 20 to which a transfer clock phi2 is applied. In a CCD tapped delay line, when a bias voltage VB fed to the gate electrode 60 is specified, since a potential gradient is caused in transferring a signal charge Qsig beneath the gate electrode 16 of the next stage from the tap addition part, the transfer efficiency is improved.
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