发明名称 DECODER
摘要 PURPOSE:To decrease the scale of hardware and to quicken the decoding speed by combining a mode discriminating means for the hardware and a mode discriminating means for software. CONSTITUTION:A decoder consists of the 1st mode discrimination circuit 1, the 2nd mode discrimination circuit 2, a selector 3, a decoder circuit 4, a change point detection circuit 5 and a timing control circuit 6. Hardware P of the 1st mode discrimination circuit 1 discriminates the vertical mode at a high speed to the mode having a high frequency of appearance. Further, the software of the 2nd mode discriminating circuit 2 discriminates the mode other than the vertical mode at a low speed to the mode with a low frequency of appearance. The selector 3 selects either the 1st mode discriminating circuit 1 or the 2nd mode discriminating circuit 2 according to a selection signal outputted from the 1st mode discrimination circuit 1 and gives an output.
申请公布号 JPS61142868(A) 申请公布日期 1986.06.30
申请号 JP19840265591 申请日期 1984.12.17
申请人 NEC CORP 发明人 USUBUCHI TOORU
分类号 H04N1/417 主分类号 H04N1/417
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