发明名称 INTERRUPTION PROCESSING SYSTEM
摘要 PURPOSE:To modify an external interruption request depending on the internal state of a processor by outputting an interruption vector designating an entry point of an interruption processing routine and an interruption request to a processor from an interruption request controller. CONSTITUTION:When any of external interruption requests 1 is active, the interruption controller 3 generates an interruption vector and transmits it to a sequencer 7 of a processor 6 via a signal line 4. The sequencer 7 loads an interruption vector on a program counter 8. When the interruption vector is an entry point of a corresponding processing routine in an instruction memory 9, the processing is started by the next instruction cycle. Further, the processing is started after two instruction cycles even for a pointer to a jump table to the processing routine. In rewriting the content of a status register 10 in the processing routine, even when the same external interruption request 1 is active, the other processing routine is started while the processor 6 does not sense the internal state.
申请公布号 JPS61151745(A) 申请公布日期 1986.07.10
申请号 JP19840273134 申请日期 1984.12.26
申请人 NEC CORP 发明人 AKATA MASAO
分类号 G06F9/48;G06F9/46 主分类号 G06F9/48
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