| 摘要 |
PURPOSE:To use just a single column decoder and to improve the integration degree and the economical performance by giving the high-speed address designating data to a pointer which connect under control a latch connected to a bit wire to a high-speed reading data bus from an output terminal of an ordinary reading column decoder. CONSTITUTION:The output terminals of bit lines BLi, BLi+1... of an ordinary reading column decoder CD1 are connected to the high-speed reading pointers SRi, SRi+1... respectively. Then the high-speed address designating data are applied to the pointers SRi, SRi+1... from said output terminals. Thus a gate G3 is controlled and the storage contents of a memory cell for word lines selected and held by latches FFi, FFi+1... are outputted successively and serially to a high-speed reading data bus SDB. In such constitution, a high-speed reading column decoder is omitted. Thus just a single decoder suffices to improve both the integration degree and economical performance of a semiconductor memory device.
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