| 摘要 |
PURPOSE:To scale down a circuit size and to reduce the time delay from the input of input data to its storage on a memory medium by regulating the recording pattern of a recording medium by an input data pattern before encoding. CONSTITUTION:An encoding circuit 7 of a write timing compensation system is constituted of a four-staged shift register 7a which stores input data, an encoded data combining circuit 7b, which generates encoded data according to the contents of the register 7a, and a word length counter 7c showing the word length of the input data in the midst of encoding. The register 7a is incorporated in an eight-bit shift register 14 with a write clock 1 and the input data 2 as an input, and a compensating amount deciding circuit 15 is connected to the register 14 and the counter 7c. Moreover a delay element 10 is connected to the circuits 7c and 15. Then the output of the circuit 15 and that of delayed and encoded data 4a-4c from the delay element 10 are ORed, and a write current generating circuit 16 outputs a recording pattern after the ORed output is added in an adder circuit 12.
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