| 摘要 |
PURPOSE:To make it possible to efficiently accomodate and process all kinds of and a lot of different speed circuit terminals, by supervising idle data cells in the buffer area in common and in the lump as to all the circuit terminals, and dynamically controlling the assignment of the idle data cells. CONSTITUTION:After initializing, the data units I37-III39 are inputted from the circuit terminal #i. Data 37-39 are connected with a chain to the idle data cells which have been taken out in order from the idle data cell queue by the input controlling part, and are stored. The data cells 40-42, 43-46, 47-48 correspond to the units I-III, respectively. In this way, a data which has been stored in the buffer area is output to the outside of the memory, after processing. As a result, the data cell becomes idle, is released from the chain connected by the input/output controlling part, and if is added after the end cell of the queue of the idle cell. And, the pointer of the control area is updated by being accompanied by release of the data cell and addition to its idle data cell queue. |
