发明名称 TIMING PULSE GENERATING CIRCUIT
摘要 PURPOSE:To generate a timing pulse of a high speed by making a memory scanning circuit group step by modulo by a stepping pulse distributing circuit, controlling a selecting circuit by a stepping pulse and selecting an output from a counting value memory, whenever a coincidence detecting output is generated. CONSTITUTION:As for a stepping pulse distributing circuit and a selecting circuit, whenever a coincidence detecting output is outputted from a coincidence detecting circuit 12, a stepping pulse in a stepping pulse distributing circuit 22 is varied as 00 01 11 00. On the other hand, this 2 bit output is inputted to a decoder 34 in a selecting circuit 2, four kinds of outputs are generated alternatively and successively, four AND gates 35 become open successively and cyclically and the corresponding counting value and information which forms a pair with said value are sent through a OR gate 36 to the coincidence detecting circuit 12 and a pulse forming circuit 14, respectively. A selection timing by the selecting circuit 21 is generated at an equal speed with a reference clock CLK, but counting value memories 13-1-13-4 are operated slowly at a period (t). In this way, a timing pulse of a high speed can be generated.
申请公布号 JPS61214610(A) 申请公布日期 1986.09.24
申请号 JP19850054107 申请日期 1985.03.20
申请人 FUJITSU LTD 发明人 HAMADA SHIGERU
分类号 H03K3/78;H03K5/15;H03K5/156 主分类号 H03K3/78
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