发明名称 ARITHMETIC AND LOGICAL UNIT
摘要 PURPOSE:To improve a data processing speed, and to simplify the generation of a program by executing a converting instruction of a bit train for constituting a data, by one instruction. CONSTITUTION:An instruction for converting the sequence of a bit train is formed by an instruction code part 20, an address operand in a memory 12 in which sequence converting command instructing information has been stored, an operand 22 of an address in which a data which becomes a converting object has been stored, and an operand 23 for storing the number of words to be converted. In this state, when a bit train converting instruction is received in the course of execution of a program, the conversion processing of a bit train is executed by one instruction by referring to said instruction code.
申请公布号 JPS61223938(A) 申请公布日期 1986.10.04
申请号 JP19850063782 申请日期 1985.03.29
申请人 CANON INC 发明人 SUGINO TOSHIO
分类号 G06F7/00;G06F7/76;G06F9/30;G06F9/315 主分类号 G06F7/00
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