2/(2N+1) FREQUENCY DIVISION CIRCUIT

摘要

PURPOSE:To obtain an all digital simple circuit by providing the 2nd shift register shifting an input pulse by a leading edge of an opposite polarity to the 1st shift register by one clock and a circuit obtaining an AND output between an output of the 2nd shift register and an output of a 1/(2n+1) frequency division circuit. CONSTITUTION:A pulse having nearly 1:1 of duty is fed to an input terminal 1 as shown in figure (a). A 1/3 frequency division circuit 2 frequency-divides the frequency of the applied pulse into 1/3 to output a pulse where the ratio of high level period and low level period is 2:1 as shown in figure (b). An output (figure b) of the 1/3 frequency division circuit 2 and an output (figure d) of the 2nd shift register 4 are ANDed by an AND circuit 5, and an output pulse shown in figure (e) is obtained at an output terminal 6. The 3 periods (e.g., a period of t2-t8) fed to the input terminal 1 in the input pulse have pulses of two periods and the circuit constitutes a 2/3 frequency division circuit.