发明名称 CLOCK EXTRACTING CIRCUIT
摘要 PURPOSE:To improve various characteristics of a capture ranger, a lock range or a pull-in time, etc. by bringing an envelope detecting output of reproducing data to waveform shaping and controlling a lock of a PLL. CONSTITUTION:An envelope signal of reproducing data which has been detected by an envelope detecting circuit 10 and brought to waveform shaping is processed by a tracking comparator 11 whose threshold level is variable in accordance with an envelope level, and a random walk filter 12 which can eliminate freely a whisker noise, etc. There is a drop-out of a result of this processing, and also, even with respect to a reproducing RF signal whose level is low, a charge pump circuit 7 for locking a PLL5 to a closed loop by a signal corresponding to a good part of its signal becomes an operating part. Accordingly, a capture ranger characteristic and a lock range characteristic related to a frequency range of a voltage control oscillator 9 of the PLL, the pull-in time is shortened, and a synchronizing clock is extracted quickly and exactly.
申请公布号 JPS61243988(A) 申请公布日期 1986.10.30
申请号 JP19850085863 申请日期 1985.04.22
申请人 SONY CORP 发明人 EBATA KAZUYOSHI
分类号 G11B20/14;H03K5/00 主分类号 G11B20/14
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