发明名称 CONTROL SYSTEM FOR IDLE AREA OF EXTERNAL MEMORY
摘要 PURPOSE:To shorten a searching time and to reduce the conversion into scraps with a hierarchical bit map by controlling the idle state with plural pairs of bits defined as a unit. CONSTITUTION:For the bit map 21 of level 0, the bits (x01-x0n) have the 1:1 correspondence to the areas (y1-yn) of fixed sizes forming an external memory 1 respectively with a bit defined as a unit. The bit values (0)2 and (1)2 means the presence and absence of an idle area respectively. The bit maps 22 and 23 of levels 1 and 2 define two bits as a unit and each of bits (x11-x1m and x21-x2l) corresponds to two units of the bit map of a level lower by 1 step. Then the bit values (00)2, (01)2, (10)2 and (11)2 mean that all areas are idle, an idle area exists at a level lower by 1 step, an idle area exists at a level lower by 2 steps and all areas are busy respectively.
申请公布号 JPS61253530(A) 申请公布日期 1986.11.11
申请号 JP19850095409 申请日期 1985.05.07
申请人 HITACHI LTD 发明人 TANAKA MAKIO
分类号 G06F12/00;G06F3/06;G06F12/02 主分类号 G06F12/00
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