发明名称 PHASE LOCKED LOOP CIRCUIT
摘要 PURPOSE:To eliminate enough a pulsative noise generated in a phase comparator, and a noise generated in a loop, and also to obtain a PLL circuit whose modulation characteristic is flat and excellent, by inserting and connecting a phase equalizer for correcting a phase characteristic of a low-pass filter, between the low-pass filter and a voltage controlled type oscillator. CONSTITUTION:Between a low-pass filter 5 and a voltage controlled type oscillator 6, a phase equalizer 10 for correcting a phase characteristic of the low-pass filter 5 is inserted and connected. In a transfer characteristic Es of this phase equalizer 10, an amplitude characteristic is denoted as I (the gain is I against a frequency of a signal), and a phase characteristic is set to a characteristic reverse to the phase characteristic of the low-pass filter 5. In other words, the product Fs.Es of the transfer characteristics of the low-pass filter 5 and the phase equalizer 10 is determined by a transfer characteristic F2, therefore, the phase characteristic becomes flat, and also becomes only a prescribed delay quantity. Accordingly, even in case is a cut-off frequency of the low-pass filter 5 is lowered, and it is brought close to a natural frequency (fn) of a PLL circuit, a modulation characteristic M's becomes flat by an effect of the phase equalizer 10, and an excellent characteristic can be obtained.
申请公布号 JPS61274406(A) 申请公布日期 1986.12.04
申请号 JP19850114193 申请日期 1985.05.29
申请人 MITSUBISHI ELECTRIC CORP 发明人 YOKOI YUJI
分类号 H03L7/18;H03D3/00 主分类号 H03L7/18
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