| 摘要 |
PURPOSE:To simplify a sequence control part by performing the parallel processing functions of continuation/termination control of a transmission and reception sequence and buffer access control by one common count register including an output value compensating cirvuit. CONSTITUTION:A common counter circuit 50 outputs a value, which is obtained by adding (01)16 to a common counter value 115, as a data count value 102. A compensating circuit 60 outputs the value, which is obtained by adding (01)16 to the common counter value 115, and the common counter value 115 selectively as a buffer address value 107 at the data transmission operation time and the data reception operation time respectively. The common counter circuit 50 outputs the common counter value 115 as a report value after transfer. Since the high-speed data transfer cycle is realized with only the update control of one common counter, the synchronous update control which controls updates of two count registers without any out-of-synchronisum is unnecessary in the sequence control part.
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