| 摘要 |
PURPOSE:To obtain a large frequency division number including a prime number with less number of components by using a counter, the 2nd NAND gate generating an inhibition signal whose width depends on a D-FF and the 1st NAND gate blocking the clock pulse with the output of the 2nd NAND gate so as to apply frequency division. CONSTITUTION:The 1st gate 6 provided to an input terminal of the counter 7 is controlled by the inhibition signal obtained from the 2nd gate 9. In setting the width of the inhibition signal depending on the state of the D-FF 8, the 1st gate 6 blocks clock pulses with an optional number (m). As a result, the clock pulse is frequency-divided into 1/(m+m).
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