发明名称 INSTRUCTION PREFETCHING CONTROL SYSTEM
摘要 PURPOSE:To suppress useless prefetch of instruction, to reduce a load and to improve performance in an instruction control device by suppressing a reading request from a main storage device at the detection of a branch instruction and releasing said suppression at the completion of the execution of the branch instruction. CONSTITUTION:When prefetch of instruction inputted to an instruction buffer 2 is decoded by a decoder 8 and the existence of a branch instruction is detected, an FF 10 is turned on and OR between an output signal of the decoder 8 and an output signal of the FF 10 is found out by an OR circuit 12. The output signal of the OR circuit 12 is functioned as a suppressing signal to a NAND circuit 13 to suppress an instruction prefetch request signal 7. At the completion of the execution of the branch instruction, the suppressing status is released.
申请公布号 JPS61286930(A) 申请公布日期 1986.12.17
申请号 JP19850128607 申请日期 1985.06.13
申请人 FUJITSU LTD 发明人 KABEMOTO AKIRA;SATO MASAO
分类号 G06F9/38 主分类号 G06F9/38
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