| 摘要 |
Parallel-series converter having a plurality of parallel inputs and comprising a combining arrangement having a plurality of inputs equal in number to the plurality of parallel inputs of the parallel-series converter, and a series output, each parallel input being connected via the series arrangement of a terminating impedance and a transmission line to a respective one of the inputs of the combining arrangement, the delay times of the individual transmission lines having respective different magnitudes according to an arithmetical progression, the junction between each terminating impedance and the associated transmission line being connected to a short-circuited transmission line having a length lambda /2, where lambda is the wavelength of the desired output frequency of the parallel-series converter, each original pulse, as applied to the input of the relevant short-circuited transmission line appearing after a short period of time, with a delay and in inverted form at the same input, such that the original pulse, during the time in which the original pulse, during the time it is overlapped by the inverted pulse, is wholly, or substantially wholly, eliminated.
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