发明名称 |
Method for fabricating stacked CMOS transistors with a self-aligned silicide process |
摘要 |
A method for siliciding interconnects on a vertically integrated device utilizing stacked CMOS technology includes a step for blocking off the p-channel devices. This blocking step is utilized to block the p-channel device in a stacked CMOS pair prior to forming titanium di-silicide on the exposed polysilicon interconnects. A mask is formed on the top polysilicon layer that forms the p-channel device and then patterned to remove the mask and the top polysilicon layer to expose the underlying polysilicon layers. A sidewall oxide is then formed to completely seal the p-channel devices and then the exposed silicon and polysilicon surfaces subjected to a self-aligned silicide process.
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申请公布号 |
US4656731(A) |
申请公布日期 |
1987.04.14 |
申请号 |
US19850762657 |
申请日期 |
1985.08.05 |
申请人 |
TEXAS INSTRUMENTS INCORPORATED |
发明人 |
LAM, HON W.;SUNDARESAN, RAVISHANKAR |
分类号 |
H01L21/8238;H01L21/336;H01L21/768;H01L21/822;H01L21/8234;H01L27/088;H01L27/092;H01L29/78;H01L29/786;(IPC1-7):H01L21/88;H01L27/02 |
主分类号 |
H01L21/8238 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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