| 摘要 |
PURPOSE:To obtain a high speed access by providing four pairs of switching transistors between the same number of four output buffers as I/O buses, main amplifiers and only one output driver. CONSTITUTION:phiOP and phiOP1 are also activated by the activation of CAS, and the phiOP activates data output buffers 1-5-1-8 with the data of I/O1, (the inverse of I/O1)-I/O4, and (the inverse of I/O4) amplified by a main amplifier. Activated four data output buffers amplify four pairs of internal I/O pairs. The phiOP1 activates a read out selection gate and selects and activates either of phiRG1-phiRG4 corresponding to either activated signal out of inputted phiNG1-phiNG4, and turns on either of switching transistor pairs QR12/QR16-QR42/ QR46. Thereby, out of the data amplified with the four data output buffers, only one datum is transmitted to DO and (the inverse of DO) through a pair of switching transistor pair which hassbeen turned on. The DO and (the inverse of DO) drive data output driving transistors Q01 and Q02, outputting the data to a DATAOUT.
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