| 摘要 |
PURPOSE:To obtain an output signal synchronously with an input signal by generating several delay signals by a delay line from an output of a fixed frequency oscillator and using a signal from a phase comparator so as to select one delay signal among them. CONSTITUTION:When the phase of an input signal 1 is advanced from that of a selection signal 12, the phase comparison circuit 2 outputs an up signal 3 and an unlock signal 4 to an up-down counter 5, causing the counter 5 to count up so as to allow a data selector 11 to select one of one selection signal 9-0 sequentially toward the direction with less delay through a counter output signal 6. Thus, the phase of the selection signal 12 and the delay signal 15 is advanced in a direction to be approached to the phase of the input signal 1 gradually. On the other hand, when the phase of the input signal 1 is delayed more than the phase of the delay signal 15, the data selector 11 selects one by one selection signal 9-0 sequentially in a direction increasing the delay. Thus, the phase of the selection signal 12 and the delay signal 15 is retarded gradually in a direction being approached to the phase of the input signal 1.
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