| 摘要 |
PURPOSE:To attain application as a digital delay line having optional delay length by providing a delay circuit between a data input part and a write data bus and setting the delay amount of the delay circuit at a proper level. CONSTITUTION:A control circuit 1 inputs a applied reset signal RST, writing clock WCK and reading clock RCK and outputs internal control signals RST', WCK' and RCK' respectively. The signal RST' is inputted to address pointers 3-6 respectively and the writing and reading actions are initialized in different fixed addresses by the signal RST' respectively. In other words, input data Din is written on a dual port cell array 7 after a delay set to a delay circuit 10 in a writing mode. In this case, the delay length of the circuit 10 is set so that coincidence is secured between the address which is used when the valid write and inputted first after resetting is written on the array 7 via the data 10 and the address where the read data is set. Thus it is possible to form a circuit that has the variable delay length in response to the resetting interval.
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