| 摘要 |
PURPOSE:To eliminate the loss of a readout voltage due to variation in substrate potential by providing a couple of bit lines with a dummy capacitor having the same capacity with a memory capacitor and equalizing level during a precharging period. CONSTITUTION:Bit lines BL1 and the inverse of BL1 are provided with the dummy cell 3 having the same capacity with the memory cell 4 and signal levels of the bit lines BL1 and the inverse of BL1 are charged in dummy capacitors C6 and C7 during an active period. When sense operation in the actice period is completed, an unselected dummy word line DWL1 is held at high level and the ground level or a Vu level is written in the dummy capacitors C6 and C7 from the bit lines BL1 and the inverse of BL1. Further, the dummy capacitors C6 and C7 are equalized during the precharging period to reduce the level to 1/2Vu. Consequently, a dynamic RAM is obtained which has no lose of the readout level and does not increase in access time even when the substrate potential does not varies.
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