Conditional-carry adder for multibit digital computer

摘要

A multibit digital adder is shown wherein a pair of carry generating circuitries is disposed between single adders for each bit in the digital numbers to be added, each one of such carry generating circuitries being responsive to a different carry-in signal and to the level of the bits applied to the associated single bit adder to produce the proper carry-in signal to the following single bit adder.