发明名称 FORMING METHOD FOR WIRING OF SEMICONDUCTOR INTEGRATED CIRCUIT
摘要 PURPOSE:To remove the possibility of a short circuit due to burrs between wiring layers by introducing an ion milling process by a rare-gas ion shock between a metallic-film forming process and a life-off process when a metallic wiring or an electrode is processed by using a lift-off method. CONSTITUTION:A wiring or an electrode pattern is formed onto a semiconductor crystal substrate 1 by employing a phot-resist 2 through photolithography. A metallic film consisting of a metallic wiring material such as Al is attached to a surface section through evaporation. A metal attached surface is irradiated by rare-gas ion beams having kinetic energy of 500eV at the incident angle of 45 deg. to the normal of the surface of the semiconductor crystal substrate, and a metallic section on the side surface 2A of the photo-resist 2 is polished. The ion beams of an inert gas such as Ar<+> are used as the rare-gas ion beams. When the metal on the side surface 2A of the photo-resist 2 is removed in this manner, the photo-resist 2 is melted by employing an organic solvent, and an unnecessary metal on the photo-resist 2 is lifted off.
申请公布号 JPS62163340(A) 申请公布日期 1987.07.20
申请号 JP19860004682 申请日期 1986.01.13
申请人 SUMITOMO ELECTRIC IND LTD 发明人 MIYANO NAOYA;EHATA TOSHIKI
分类号 H01L21/3205 主分类号 H01L21/3205
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