发明名称 DECODER CIRCUIT
摘要 PURPOSE:To attain a 1-3 decoder circuit with a simple constitution by using an input circuit having a different threshold level. CONSTITUTION:The threshold level of an inverter 1 is set higher than the threshold level of an inverter 2. When the input level is an intermediate level 'N' between the level at which both inverters 1, 2 are logic 0 and logic 1, the output of the inverters 1, 2 is respectively logic 1 and logic 0. Logic 1 is outputted from an AND gate 3 only when the input level is a level at which both inverters 1, 2 are logic 0 in the decoder, logic 1 is outputted from an exclusive OR 4 only when the input level is the intermediate level 'N' and logic 1 is outputted from a NOR gate only when the input level is a level at which both inverters 1, 2 are logic 1, then the decoder acts like the 1-3 decoder.
申请公布号 JPS62176333(A) 申请公布日期 1987.08.03
申请号 JP19860019417 申请日期 1986.01.30
申请人 NEC CORP 发明人 KOYADA HIROSHI
分类号 H03M7/00 主分类号 H03M7/00
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