发明名称 |
SIGNAL BYPASS SYSTEM FOR PARALLEL COMPUTER |
摘要 |
PURPOSE:To omit the intervention of the data processing part of a computer and to increase the communication speed between computers, by setting a bypass state holding circuit provided separately from the data processing part of the computer and bypassing the input and the output of the computer. CONSTITUTION:When a bypass state holding circuit 14 is set, communication data, etc. never pass through a data processing part 15 thereafter. This can omit such a conventional case where the communication data received by the part 15 is transmitted again. Thus the communication of data is possible with no delay. Furthermore, it is enough for a bypass circuit 12 to make just a signal route conductive by providing an input selecting circuit 11 and an output selecting circuit 13. Thus a bypass is attained with a small quantity of simple hardware.
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申请公布号 |
JPS62180456(A) |
申请公布日期 |
1987.08.07 |
申请号 |
JP19860021831 |
申请日期 |
1986.02.03 |
申请人 |
NIPPON TELEGR & TELEPH CORP <NTT> |
发明人 |
SHIMADA SHIGEO;OGAWA YOSHIO;ISHIKAWA TSUTOMU |
分类号 |
G06F15/16;G06F15/173;G06F15/80 |
主分类号 |
G06F15/16 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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