Data read circuit for use in semiconductor memory device.

摘要

A data read circuit for use in a semiconductor memory device including: an input node (a) operatively connected to a bit line (BLo); an output node (d) for outputting a read-out signal; a first transistor (Tr3) connected between the input node and the output node and turned ON and OFF in accordance with a potential of the bit line connected to a selected memory cell transistor (Tcoo); a second transistor (Tr6) connected to the out-put node and turned ON for a predetermined period after an address signal is changed; and a third transistor (Tr'4) connected to the second transistor in parallel and turned ON and OFF in accordance with the read-out signal so that the third transistor is turned OFF when the selected memory cell transistor is turned ON.