| 摘要 |
PURPOSE:To heighten responding capacity of block load at the time of sweeping out avoiding busy of a bus and a main memory circuit by providing a store buffer memory, storing sweep out data temporarily in the store buffer memory, and rewriting the stored contents in the main memory circuit after reading and transferring fetch data. CONSTITUTION:By providing a store buffer memory 5 and transferring sweep out data to the store buffer memory 5 during reading of fetch data, disturbance of transfer cycle of fetch data is prevented. Further, by storing the content of the store buffer memory 5 in a main memory circuit 6 after reading of fetch data, factors that delay fetching operation are removed. Data transfer to the store buffer memory 5 is made utilizing vacant time from the time of sending out of a fetch address to read out and getting on a bus of the data. As writing back from the store buffer memory to the main memory circuit 6 is made lowering priority order, request to a processor and channel is not obstructed.
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