| 摘要 |
PURPOSE:To increase the space using efficiency by a method wherein multiple circuit blocks and probe connecting pads connected to multiple circuit blocks used for testing respective circuit blocks are provided on a substrate while a part of the pads are common-connected to multiple circuit blocks. CONSTITUTION:A part of probe connecting pads 3 is removed and instead another pad 3a similar to the pad 3 and an interconnection 4 are additionally provided. The removed pad 3 to be the potential of respective substrate 1 out of the potentials incident to respective circuit blocks 2 is a power supplying pad in case the circuit block 2 is a CMOS. The removed pad 3 is common- connected to the pad 3a through the intermediary of the interconnectlon 4. Through these procedures, this integration can eliminate the mutual interference in the circuit blocks 2 in case of testing respective circuit blocks 2 while decreasing the total numbers of pads 3 and 3a less than those of conventional constitution to increase the space using efficiency of substrate 1.
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