| 摘要 |
PURPOSE:To reduce the power consumption and the refresh time by applying the refresh while lots of memory arrays are made simultaneously selecting state and operating only a sense amplifier related to the selected word line at memory access. CONSTITUTION:A row decoder XDCRO, 1 use an address signal supplied from a row address buffer XADB to form selection signals for the word lines of memory arrays M0, 2 and M1, 3. Thus, word line circuits WDRVO, 2 and DWRV1, 3 make the word and dummy word lines of the corresponding memory arrays M0, 2 and M1, 3 into the selecting state. Only sense amplifiers SA0, 2 or SA1, 3 corresponding to the lines are activated at the same time and the power consumption is reduced. Then an address signal from a refresh control circuit REFC is sent to circuits SDCRO, 1 via the buffer XADB, all memory arrays M0-3 are driven at the same time to reduce the refresh time.
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