| 摘要 |
Multiresolution processing apparatus (which may be programmed as pyramid processing apparatus) comprised of a filter logic unit comprised of one or a plurality of identical interconnected programmable modules; a set of programmable multiplexers (MUX), a plurality of programmable random access-memories (RAM), and a timing and control means including an instruction memory for programming the flow of information data through and the operation of the filter logic unit, the set of MUX and the plurality of RAM. This permits a single stage to sequentially operate as each separate stage of an FSD or Burt Pyramid analyzer or of a pyramid synthesizer.
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