发明名称 COMPLEMENTARY MOS INTEGRATED CIRCUIT
摘要 PURPOSE:To obtain a highly integrated static PLA or a static decoder in a regular structure logic circuit by contracting a wiring region for connecting PMOS matrix with NMOS matrix. CONSTITUTION:A signal is input from an input signal line 1 to a matrix, the signals input to drive lines A1-A5 are logically processed by logic elements 3-5 and output to an output line 2. For example, when the logic circuit is achieved with complementary MOS, NAND logic, static, the circuit is composed of PMOS matrix 13, NMOS matrix 14 and a wiring region. Wirings 17 for connecting the PMOS 7-9 in the matrix 13 with NMOS 12 in the matrix 14 is wired over the matrixes by utilizing upper layer wirings on aluminum. The wiring region is absorbed to the matrixes to perform a highly integrated regular structure logic circuit.
申请公布号 JPS62252161(A) 申请公布日期 1987.11.02
申请号 JP19860094552 申请日期 1986.04.25
申请人 HITACHI LTD;HITACHI MICRO COMPUT ENG LTD 发明人 MASUDA HIROYUKI;NOGUCHI YOSHIKI;KAMESHIMA SHIGEHIRO;KINEBUCHI YUTAKA;TAKATORI HIROTAKA
分类号 H03K19/177;H01L21/82;H01L21/8234;H01L21/8238;H01L27/08;H01L27/088;H01L27/092 主分类号 H03K19/177
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