发明名称 STANDBY LINE SUPERVISORY CIRCUIT
摘要 PURPOSE:To increase the sampling margin at the receiving end by adopting a consittution that an M-period seudo random signal is converted into two kinds of N-bit fixed pattern signals at the sending end and the result is sampled by using a sampling pulse having a frequency being 1/N of the transmission signal speed at the receiving end. CONSTITUTION:The transmission end (A) is provided with a 1/N frequency division circuit 101 (N is an integer being 2 or over), an M-period pseudo random signal generating circuit 102, a conversion circuit 103, and a unipolar/ bipolar conversion circuit 202, and the receiving end (B) is provided with a rectifier circuit 203, a 1/2 frequency division circuit 205, a sampling pulse extraction circuit 105, a delay circuit 206, a phase comparator circuit 207 and a comparator circuit 208. At the transmission end the M-peiod pseudo rando signal is converted into two kinds of N-bit fixed pattern signals to be the receiving end samples the result by using a sampling pulse having a frequency being 1/N of the transmission signal speed. Thus, the timing margin is increased and the stable circuit not causing malfunction is obtained.
申请公布号 JPS62254541(A) 申请公布日期 1987.11.06
申请号 JP19860099254 申请日期 1986.04.28
申请人 NEC CORP;NEC ENG LTD 发明人 NAKAJIMA MASAHIRO;KASHIBA SATOSHI
分类号 H04J3/14;H04L1/00;H04L1/22;H04L25/02 主分类号 H04J3/14
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