发明名称 LOAD DECENTRALIZATION CONTROL SYSTEM FOR AUXILIARY MEMORY DEVICE OF VIRTUAL MEMORY SYSTEM
摘要 PURPOSE:To secure the substantial decentralization of load for an auxiliary memory device by using a means to store a coefficient showing the processing capacity of an auxiliary memory device serving as a secondary memory area of a virtual memory device. CONSTITUTION:The processing capacity coefficients produced from capacities of the access timers and using channels set for auxiliary memory devices 61-64 and stored in the 1st memory means are registered to processing capacity memory lists 501-531 in response to those devices 61-64 respectively. An access frequency counting means 3 counts up for each access of devices 61-64 and records these count values to access frequency recording lists 502-532. A load frequency counting means 41 counts the substantial load frequencies based on the contents of those lists 501-531 and 502-532 and records them to substantial load recording lists 503-533. A comparison means 8 compares the recorded contents of lists 503-533 with each other and selects an auxiliary memory device having the lowest load frequency to perform allocation of pages.
申请公布号 JPS62260246(A) 申请公布日期 1987.11.12
申请号 JP19860103219 申请日期 1986.05.07
申请人 NEC CORP 发明人 TAKENAGA SHINKICHI
分类号 G06F12/08;G06F12/10 主分类号 G06F12/08
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