发明名称 ACCESS CONTROL CIRCUIT FOR CACHE MEMORY
摘要 PURPOSE:To prevent the contents of a main memory and those of a cache memory from becoming incoincident even by using a system bus to other bus masters. CONSTITUTION:When the other bus master writes data in the main memory through the system bus SB, a bus comparison part 12 compares the contents of a physical tag part 10 designated by P-INDEX showing a physical address PA on the system bus SB with P-TAG showing the physical address PA. If the compared result is coincident, and even an invalid display part V shows validity, the contents of an index part 11 at the address designated by the P-INDEX showing the physical address PA are read. Since the value is fitted for the L-INDEX showing a logical address LA corresponding to the physical address PA on the system bus SB, a cache control part 30 invalidates the invalid display part V in a logical tag part 20 designated by the L-INDEX. Thus, a CACHE dissident with the contents of the main memory is invalidated.
申请公布号 JPS62266634(A) 申请公布日期 1987.11.19
申请号 JP19860109931 申请日期 1986.05.14
申请人 YOKOGAWA ELECTRIC CORP 发明人 ITO MASAHIRO
分类号 G06F12/08 主分类号 G06F12/08
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