发明名称 |
Digital integrated circuits |
摘要 |
A digital integrated circuit is described in which the internal registers are organized into a number of serial shift paths to facilitate testing. Each path has a number of modes; USER, HOLD, SHIFT and SELF-TEST modes. Shifting of a path is achieved by putting the path into HOLD mode and then, at each of a series of transfer pulses (TR), putting the path into shift mode for one clock beat. This allows the shifting to be performed at a lower rate than the internal clock rate of the chip; in particular, it can be performed at a rate compatible with a relatively slow diagnostic processor.
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申请公布号 |
US4730317(A) |
申请公布日期 |
1988.03.08 |
申请号 |
US19860882947 |
申请日期 |
1986.07.07 |
申请人 |
INTERNATIONAL COMPUTERS LIMITED |
发明人 |
DESYLLAS, PETER L. L.;NAVEN, FINBAR |
分类号 |
G01R31/3185;(IPC1-7):G01R31/28 |
主分类号 |
G01R31/3185 |
代理机构 |
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代理人 |
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主权项 |
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地址 |
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