| 发明名称 |
Logic full adder circuit |
| 摘要 |
A logic circuit incorporating carry look-ahead in which efficiency can be achieved regarding the hardware for generating the sum signals and carry signals by a suitable choice of the adder gate, making use of the already present signal &upbar& a1x &upbar& bi which is used for generating the carry look-ahead signal.
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| 申请公布号 |
US4730266(A) |
申请公布日期 |
1988.03.08 |
| 申请号 |
US19850698055 |
申请日期 |
1985.02.04 |
| 申请人 |
U.S. PHILIPS CORPORATION |
发明人 |
VAN MEERBERGEN, JOZEF L.;VEENDRICK, HENDRIKUS J. M.;WELTEN, FRANCISCUS P. J. M.;VAN WIJK, FRANCISCUS J. A. |
| 分类号 |
G06F7/501;G06F7/50;G06F7/508;(IPC1-7):H01L27/02 |
主分类号 |
G06F7/501 |
| 代理机构 |
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代理人 |
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