| 摘要 |
A fail memory equipment has a plurality of memory blocks which can be changed in their combinations serially or in parallel in accordance with the capacity of a memory to be tested, the number of channels to be tested simultaneously and the testing speed. The single fail memory equipment operates in an interleave fetching mode for a high speed test, in a parallel fetching mode for a multi-channel test or in a serial fetching mode for testing a memory of a large capacity, thereby realizing a high speed test, a large capacity memory test and a simultaneous multi-channel test.
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