| 摘要 |
PURPOSE:To make the number of times of traceback in one cycle once and to enhance the speed-up of decoding by providing two bus memories, in one of which the result of an addition, a comparison and a selection is stored and in other of which all the frame lengths during one frame are made to be traced back. CONSTITUTION:In the control circuit 31 on the transmission side of a system, according to the pause of the frame from a frame synchronizing pattern generation circuit 3 a register is reset in a convolutional encoder 4 at the time of starting a frame and the end data is added at the time of completing the frame. Every completed frame, a speed conversion circuit 2 inserts a frame pattern and gives pauses to the frame so as to transmit to a reception side from a modulator 5. The signal is demodulated 8 and the result obtained by addition, comparison and selection as for one frame is stored in the first and second bus memory circuits 21 and 22 of an output buffer circuit 25. And the memories 21 and 22 are made to be traced back with a traceback control circuit controlled by a frame synchronizing circuit 15.
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